The present invention relates to a system for simulating an electronic circuit making it possible to simulate the electrical behaviour in time of a given electronic circuit subject to given electrical operating conditions.
Conventionally, the simulated electronic circuit is described as being a network having a certain number of nodes and branches, each having one or more components of the resistor, capacitor, inductor, transistor or similar type. This is followed by the definition of the electrical supply conditions of this electronic circuit, as well as the shape of the electrical control signal or signals applied to one or several inputs of said circuit.
Thus, a simulation system receives a first sequence of coded electrical signals representing the description of the electrical circuit, i.e. indicating the nodes of the network, the branches connecting two of these nodes in each case and the components of each branch, a second sequence of coded electrical signals representing the electrical operating conditions of the circuit, a third sequence of coded electrical signals representing the function existing between the voltage applied to the terminals of each of the circuit components (resistor, capacitor, inductor, transistor, etc) or time derivative and the current flowing through said component, as well as a fourth sequence of coded electrical signals indicating the nodes for which it is necessary to carry out the simulation of the electrical state at a given time t, together with the determination of the time interval .DELTA.t for the following simulation performed at time t+.DELTA.t, the electrical signals of said sequences being in general binary signals.
The simulation systems make it possible to evaluate the probable performances of an electronic circuit without it being necessary to physically realize said circuit. They also make it possible to rapidly test different embodiments of a circuit being developed. Therefore simulation systems are used for the development of electronic circuits.
Each simulation system is essentially defined by two parameters, namely the system of differential equations used for modeling the electronic circuit and the method used for solving this system of differential equations. Among the most widely used representations, reference can be made to the Euler, trapezium and GEAR models. For each of these models, it is possible to choose as a function of the simulated electronic circuit type and the desired accuracy of calculating the potentials of the nodes, models of order 1, order 2 or a higher order, i.e. respectively only taken account of the first derivative of the potential, the first two derivatives of the potential or higher order derivatives.
The model chosen to represent an electronic circuit does not generally constitute a characteristic of the simulation system. However, the choice of a resolution method for the model is a characteristic of a simulation system and defines its performance and capacity.
Electronic circuit simulation systems are generally placed in three generations, each defined by the method used for solving the system of differential equations representing said electronic circuit. The first generation corresponds to the first simulation systems developed in the 1960's. The simulation systems developed in the 1970's roughly correspond to the second generation. A first example of such a simulation system is described in the article: "SPICE 2: a computer program to simulate semiconductor circuits", by L. N. Nagel, University of California, Berkeley, May 1975.
In this simulation system, the system of differential equations representing the electronic circuit is solved by the Newton method. This method uses Jacobian computations to solve the system of differential equations, said Jacobian being a matrix of p.times.p elements for an electronic circuit with p nodes, and inverse of Jacobian computations. The potential of each node of the electronic circuit is then directly obtained by means of the inverse of the Jacobian matrix.
The inversion of the Jacobian matrix represents a considerable calculation volume. It should be noted that this volume increases with the square of the size of the simulated circuit, which in practice limits the use of this simulation system to electronic circuits not exceeding roughly 50 transistors, because for more complex electronic circuits the calculation time becomes prohibitive.
The article "MOTIS--A MOS timing simulator" by B. R. Chawla, H. K. Gummel and P. Kozak, which appeared in IEEE transactions, vol CAS-22, No 12, pp 901-910, December 1975 describes another second generation simulation system which does not use the Newton method. One of the characteristics of this simulation system consists of ignoring the coupling between some nodes and in particular the weak back couplings.
This makes it possible to simplify the system of differential equations modeling the simulated electronic circuit and consequently reduce the volume of the calculations making it possible to obtain the potentials of the nodes. As a result of ignoring some couplings the disadvantage is encountered of reducing the accuracy over the calculated potentials to about 10%, and of restricting the use of this simulation system to logic circuits, i.e. circuits not having back couplings.
A second characteristic of this simulation system is the sequencing of the nodes, which consists of classifying the nodes in the order in which they receive an electrical signal propagating in the simulated electronic circuit and calculating the potentials of the nodes of the circuit in this order. This sequencing is necessary due to the approximation caused by eliminating the weak couplings.
Finally a third generation simulation system is known in which the potential of each node is determined by an iterative calculation on each equation of the differential equation system. This simulation system is more particularly described in the articles "The Waveform Relaxation Method for time domain analysis of large scale integrated circuits" by E. LELARASME, A. E. RUEHLI and A. SANGIOVANNI-VINCENTELLI, which appeared in IEEE Transactions of CAD, vol CAD-1, No 3, July 1982, pp 131-145 and "RELAX a new circuit simulator for large scale MOS integrated circuits" by E. LELARASME and A. SANGIOVANNI-VINCENTELLI published at the 19th DAC conference in 1982.
The resolution method used in this simulation system is called the waveform relaxation method or WRM, by reference to successive iterations performed in order to obtain the potential in one node of the circuit.
Before describing the operation of this known simulation system with respect to the flow chart of FIG. 1, a definition will be provided of the notations used in the remainder of the description for representing the simulated electronic circuit.
The state of this electronic circuit can be represented by the implicit differential equation F(t, V, V, V, . . . )=0, in which t is time, V=(.sup.1 v, .sup.2 v, . . . .sup.p v) represents the potentials of each of the p nodes of the circuit, V is the first derivative of V and V is the second derivative of V.
Equation F(t, V, V, V . . . )=0 is a group of p differential equations and the order of this equation is generally between 1 and 6. Solving this equation for a time t determines the potentials (.sup.j v).sub.1 .ltoreq..sub.j .ltoreq..sub.p of the nodes of the electronic circuit at this time.
Throughout the remainder of the description, index n which is between 1 and N designates the successive calculating times of the electronic circuit state, the index i indicates the relaxation iteration number during the calculation of the potential of a node and index j, between 1 and p, designates one of the nodes in an electronic circuit with p nodes. On the basis of these notations, the value of the potential of node j at time n obtained in the ith iteration is designated .sup.j v.sub.n.sup.i.
The flow chart of FIG. 1 illustrates the processing performed by the known WRM simulation system for calculating the potential in each node of a simulated electronic circuit.
This processing comprises a sequence of interrogations (or propositions), whose content is descrbed in a diamond shaped box with one input and two outputs, one being used in the case of an affirmative answer, the other in the case of a negative answer and a sequence of operations, whose content is described in a rectangle with one input and one output. Each of these propositions and operations is designated by a numerical reference. The flow chart also has a begin declaration designated 2 and an end declaration designated 36.
The operations performed are as follows:
4: initialization of the iteration index i at value 1,
6: initialization of the node index j at value 1,
8: initialization of the time index n at value 1,
10: solving the equation .sup.j E(.sup.j v.sub.n.sup.i)=0, calculation of .sup.j e.sub.n.sup.i =.vertline..sup.j v.sub.n.sup.i -.sup.j v.sub.n.sup.i-1 .vertline., and storage of .sup.j v.sub.n.sup.i and .sup.j e.sub.n.sup.i,
14: allocation of the value .sup.j e.sub.1.sup.i to the variable .sup.j e.sup.i,
16: allocation of the maximum value between .sup.j e.sub.n.sup.i and .sup.j e.sup.i to the variable .sup.j e.sup.i,
20: incrementation of the time index n,
24: allocation of the value .sup.1 e.sup.i to the variable d.sup.i,
26: allocation of the maximum value between .sup.j e.sup.i and d.sup.i to the variable d.sup.i,
30: incrementation of the index of node j,
34: incrementation of the iteration index i.
The interrogations or propositions are as follows:
12: time index n equal to 1,
18: time index n equal to N,
22: node index j equal to 1,
28: node index j equal to p,
32: d.sup.i below a given threshold value .delta..
The calculation of the potential in each node of a simulated electronic circuit takes place, according to the flow chart of FIG. 1, in the following way. Firstly the iteration index i and node index j are initialized at 1. The resolution process than consists of calculating, for each time T.sub.n,1.ltoreq.n.ltoreq.N, a first value of the potential of the first node. This is obtained by solving the implicit differential equation .sup.1 E(.sup.1 v.sub.n.sup.1)=0, deduced from the first component of the vector differential equation F(t, V, V, V, . . . )=0, for each time .tau..sub.n (operation 19). This operation is then repeated for each of the p nodes. At the end of the first iteration, p.times.N potential values have been stored. These values constitute a first approximation of the potential of each node at each time. By successive iterations, these p.times.N potential values can be refined.
This iteration takes place up to the convergence of each of the p.times.N sequences (.sup.j v.sub.n.sup.1, .sup.j v.sub.n.sup.2, .sup.j v.sub.n.sup.3, . . . ), in which 1.ltoreq.j.ltoreq.p and 1.ltoreq.n.ltoreq.N. To establish whether convergence exists, for each node j and for each time T.sub.n, calculation takes place of an error term .sup.j e.sub.n.sup.i equal to .vertline..sup.j v.sub.n.sup.i -.sup.j v.sub.n.sup.i-1 .vertline. (operation 10).
This method for calculating the potential in each node and at each time of a simulated electronic circuit calls for at least two comments. Firstly the real value of the potential in a random node and at a random time in only known at the end of processing. Secondly, this method makes it necessary to store at least p.times.N potential values constituting the result of an iteration, but also p.times.N potential values calculated during the preceding iteration, in order to check whether each of the p.times.N sequences of potentials converge. Thus, this processing method requires a data memory containing at least 2.times.p.times.N potential values. It is also pointed out that even if a single sequence does not converge, a new iteration is performed for each of the p.times.N sequences, which can lead to the needless recalculation of potential values, whose associated sequences are already convergent.
The number of times N where the potential is calculated can exceed 1000, so that this resolution method requires a very large memory of approximately 1 Mbyte for an electronic circuit having roughly 50 transistors.